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is2 9gl256 256 m - bit 3.0 v page mode parallel flash memory advanced data sheet
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 2 is29gl256 h/l features ? single power supply operation - full voltage range: 2.7 to 3.6 volts read and write operations ? high performance - access times as fast as 70 ns ? v io input/output 1.65 to 3.6 volts - all input levels (address, control, and dq input levels) and outputs are determined by voltage on v io input. v io range is 1.65 to v cc ? 16 - word/ 32 - byte page read buffer ? 256 - word/ 512 - byte write buffer reduces overall programming time for multiple - word updates ? secured silicon sector (ssr) region - 512 - word/ 1024 - byte sector for permanent, secure identification - 256 - word factory locked ssr and 256 - word customer locked ssr ? uniform 64kword/128kbyte sector architecture 256 sectors ? suspend and resume commands for program and erase operations ? write operation status bits indicate pro gram and erase operation completion ? support for cfi (common flash interface) ? persistent methods of advanced sector protection ? wp#/acc input - accelerates programming time (when v hh is applied) for greater throughput during system production - protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion ? minimum 10 0 k program/erase endurance cycle s. ? package options - 56 - pin tsop - 64 - ball 11 mm x 13 mm bga - 64 - ball 9 mm x 9 mm bga - 56 - ball 7 mm x 9 mm bga ? temperature range - extended grade : - 40c to +105c - v grade (hybrid) : - 40c to +125c - auto motive grade: up to +125c general description the is29gl256 offer s a fast page access time of 25ns with a corresponding random access time as fast as 70 ns. it feature s a write buffer that allows a maximum of 256 words/ 512 bytes to be programmed in one operation, resulting in faster effective programming t ime than standard programming algorithms. this makes the device ideal for todays embedded applications that require higher density, better performance and lower power consumption. is29gl256 256 megabit ( 32768 k x 8 - bit / 16384 k x 16 - bit) flash memory page mode flash memory, cmos 3.0 volt - only advanced information
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 3 is29gl256 h/l connection diagrams figure 1. 56 - pin standard tsop (top view) note: rfu= reserved for future use 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a23 a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 rfu rfu rfu rfu a16 byte# vss dq15/a - 1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0 rfu v io 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 4 is29gl256 h/l figure 2 . 64 - ball ball grid array (top view, balls facing down) note: rfu= reserved for future use a7 a13 b7 a12 c7 a14 d7 a15 h7 vss e7 a16 f7 byte# g7 dq15 / a - 1 a1 rfu b1 rfu c1 rfu d1 rfu e1 rfu f1 v io g1 rfu h1 rfu a2 a3 b2 a4 c2 a2 d2 a1 e2 a0 f2 ce# g2 oe# h2 vss a3 a7 b3 a17 c3 a6 d3 a5 e3 dq0 f3 dq8 g3 dq9 h3 dq1 a4 ry / by# b4 wp# / acc c4 a18 d4 a20 e4 dq2 f4 dq10 g4 dq11 h4 dq3 a6 a9 b6 a8 c6 a10 d6 a11 e6 dq7 f6 dq14 g6 dq13 h6 dq6 a5 we# b5 reset# c5 a21 d5 a19 e5 dq5 f5 dq12 h5 dq4 g5 vcc a8 rfu e8 vss f8 rfu c8 a23 g8 rfu h8 rfu b8 a22 d8 v io
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 5 is29gl256 h/l figure 2 - 1. 56 - ball ball grid array (top view, balls facing down) wp#/acc
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 6 is29gl256 h/l table 1. pin description figure 3 . logic diagram pin name function a23 C C io supply voltage for input /output . byte# byte/word mode selection wp#/acc write protect / acceleration pin ( wp# has an internal pull - up; when unconnected, wp# is at v ih . ) rfu reserved for future use. not connected to anything dq0 C dq15 (a - 1) a0 C a 2 3 we # ce # ry/by # reset # byte # o e # wp#/acc v io
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 7 is29gl256 h/l table 2. product selector guide product number is29gl256 speed option full voltage range: vcc=2.7 C io =1.65 C 70ns max access time, ns (t acc ) 70 max page read access, ns(t pacc ) 25 max ce# access, ns (t ce ) 70 max oe# access, ns (t oe ) 25 block diagram we # ce # oe # state control command register erase voltage generator input/output buffers program voltage generator chip enable output enable logic data latch y - decoder x - decoder y - gating cell matrix timer vcc detector a 0 - a 2 3 vcc vss dq0 - dq15 (a - 1) address latch block protect switches stb stb ry/ by # v io
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 8 is29gl256 h/l product overview is29gl256 is 256 mb, 3.0 - volt - only, page mode flash devices optimized for todays embedded designs that demand a large storage array and rich functionality. this product offer s uniform 64 kword (128 kb) sectors and feature v i / o control, allowing control and i/o signals to operate from 1.65 v to v cc . additional feat ures include: ? single word programming or a 256 - word buffer for an increased programming speed ? program suspend/resume and erase suspend/resume ? advanced sector protection methods for protecting sectors as required ? 512 words/ 1024 bytes of secured silicon area for storing customer secured information. the secured silicon sector is one time programmable (otp) .
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 9 is29gl256 h/l t able 3 . s ector / persistent protection sector group address tables ppb group a2 3 - a1 8 sector sector size (kbytes / kwords) address range (h) word mode (x 16 ) ppb 0 0 00000 sa0 128 / 64 000000 C 00ffff ppb 1 sa1 128 / 64 010000 C 01ffff ppb 2 sa2 128 / 64 020000 C 02ffff ppb 3 sa3 128 / 64 030000 C 03ffff ppb 4 0 0 0001 sa4 128 / 64 040000 C 04ffff ppb 5 sa5 128 / 64 050000 C 05ffff ppb 6 sa6 128 / 64 060000 C 06ffff ppb 7 sa7 128 / 64 070000 C 07ffff ppb 8 00 0 010 sa8 128 / 64 080000 C 08ffff ppb 9 sa9 128 / 64 090000 C 09ffff ppb 10 sa10 128 / 64 0a0000 C 0affff ppb 11 sa11 128 / 64 0b0000 C 0bffff ppb 12 0 0 0011 sa12 128 / 64 0c0000 C 0cffff ppb 13 sa13 128 / 64 0d0000 C 0dffff ppb 14 sa14 128 / 64 0e0000 C 0effff ppb 15 sa15 128 / 64 0f0000 C 0fffff ppb 16 0 0 0100 sa16 128 / 64 100000 C 10ffff ppb 17 sa17 128 / 64 110000 C 11ffff ppb 18 sa18 128 / 64 120000 C 12ffff ppb 19 sa19 128 / 64 130000 C 13ffff ppb 2 0 0 00101 sa20 128 / 64 140000 C 14ffff ppb 21 sa21 128 / 64 150000 C 15ffff ppb 22 sa22 128 / 64 160000 C 16ffff ppb 23 sa23 128 / 64 170000 C 17ffff ppb 24 0 00110 sa24 128 / 64 180000 C 18ffff ppb 25 sa25 128 / 64 190000 C 19ffff ppb 26 sa26 128 / 64 1a0000 C 1affff ppb 27 sa27 128 / 64 1b0000 C 1bffff ppb 28 0 00111 sa28 128 / 64 1c0000 C 1cffff ppb 29 sa29 128 / 64 1d0000 C 1dffff ppb 30 sa30 128 / 64 1e0000 C 1effff ppb 31 sa31 128 / 64 1f0000 C 1f f fff ppb 32 0 01000 sa32 128 / 64 200 000 C 20f fff ppb 33 sa33 128 / 64 210 000 C 21f fff ppb 34 sa34 128 / 64 220 000 C 22f fff ppb 35 sa3 5 128 / 64 230 000 C 23f fff
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 10 is29gl256 h/l ppb group a2 3 - a18 sector sector size (kbytes / kwords) address range (h) word mode (x 16 ) ppb 3 6 0 01001 sa3 6 128 / 64 240 000 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 11 is29gl256 h/l ppb group a2 3 - a18 sector sector size (kbytes / kwords) address range (h) word mode (x 16 ) ppb 7 2 0 10010 sa72 128 / 64 480000 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 12 is29gl256 h/l ppb group a2 3 - a18 sector sector size (kbytes / kwords) address range (h) word mode (x 16 ) ppb 10 8 0 11011 sa108 128 / 64 6c0000 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 13 is29gl256 h/l ppb group a2 3 - a18 sector sector size (kbytes / kwords) address range (h) word mode (x 16 ) ppb 14 4 100100 sa144 128/64 900000 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 14 is29gl256 h/l ppb group a2 3 - a18 sector sector size (kbytes / kwords) address range (h) word mode (x 16 ) ppb 18 0 101101 sa180 128/64 b40000 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 15 is29gl256 h/l ppb group a2 3 - a18 sector sector size (kbytes / kwords) address range (h) word mode (x 16 ) ppb 21 6 110110 sa216 128/64 d80000 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 16 is29gl256 h/l ppb group a2 3 - a18 sector sector size (kbytes / kwords) address range (h) word mode (x 16 ) ppb 24 8 111110 sa248 128/64 f80000 C C C C C C C C table 4. device operating modes 256 m flash user mode table operation ce# oe# we# r e - set # wp # / acc a0 - a 2 3 dq0 - dq7 dq8 - dq15 b yte # = v ih b yte # = v il read l l h h l/ h a in d out d out dq8 - dq 14 =high - z, dq15 = a - 1 write l h l h (note 1) a in d in d in accelerated program l h l h v hh a in d in d in cmos standby v cc ? 0.3v x x v cc ? 0.3v h x high - z high - z high - z output disable l h h h l/ h x high - z high - z high - z hardware reset x x x l l /h x high - z high - z high - z notes : 1. addresses are a23 :a0 in word mode; a23 :a - 1 in byte mode. 2. if wp# = vil, on the outermost sector remains protected. if wp# = vih, the outermost sector is unprotected. wp# has an internal pull - up; when unconnected, wp# is at vih. all sectors are unprotected when shipped from the factory (the secured silicon sector can be factory prote cted depending on version ordered.) 3. din or dout as required by command sequence, data polling, or sector protect algorithm. legend l = logic low = vil, h = logic high = vih, vhh = 8.5 C 9.5 v, x = dont care, ain = address in, din = data in, dout = data out regarding to some additional operating modes such as sector lock status verification, read manufacturer code, and so on , please refer to the appendix - 1.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 17 is29gl256 h/l user mode definitions word / byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic 1, the device is in word configuration, dq0 - dq15 are active and controlled by ce# , oe# , and we# . if the byte# pin is set at logic 0, the device is in byte configuration, and only data i/o pins dq0 - dq7 are active and controlled by ce# , oe# , and we# . the data i/o pins dq8 - dq14 are tri - stated, and the dq15 pin is used as an input for the lsb (a - 1) address function. v io c ontrol the v io allows the host system to set the voltage levels that the device generates and tolerates on all inputs and outputs (address, control, and dq signals). v io range is 1.65 to v cc . for example, a v io of 1.65 - 3.6 volts allows for i/o at the 1. 65 or 3 .6 volt levels, driving and receiving signals to and from other 1. 65 or 3 .6 v devices on the same data bus. read all memories require access time to output array data. in a read operation, data is read from one memory location at a time. addresses are pres ented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive with the address on its inputs. the device defaults to reading array data after device power - up or hardware reset. to read data from the memory array, the system must first assert a valid address on a23 - a0, while driving oe# and ce# to vil. we# must remain at vih. all addresses are latched on the falling edge of ce#. data will appear on dq15 - dq0 after address access time (tacc), which is equal to the delay from stable addresses to valid output data. the oe# signal must be driven to vil. data is output on dq15 - dq0 pins after the access time (toe) has elapsed from the falling edge of oe#, assuming the tacc access time has been meet. page read mode the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 16 words/32 bytes. the appropriate page is selected by the higher address bits a23 - a 4 . address bits a 3 - a0 in word mode (a 3 to a - 1 in byte mode) determine the specific word within a page. the microprocessor supplies the specific word location. the random or initial p age access is equal to tacc or tce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tpacc. when ce# is deasserted and reasserted for a subsequent access, the access time is tacc or tce. fast page mode accesses are obtained by keeping the read - page addresses constant and changing the intra - read page addresses.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 18 is29gl256 h/l autoselect the autoselect mode provides manufacturer id, device identification, and sector protection inform ation, through identifier codes output from the internal register (separate from the memory array) on dq7 - dq0. ? the autoselect command sequence may be written to an address within a sector that is either in the read or erase - suspend - read mode. ? the autoselect command may not be written while the device is actively programming or erasing. ? the system must write the reset command to return to the read mode (or erase - suspend - read mode if the sector was previously in erase suspend). ? when verifying sector protection, the sector address must appear on the appropriate highest order address bits. the remaining address bits are don't care and t hen read the corresponding identifier code on dq15 - dq0. program/erase operations these devices are capable of severa l modes of programming and or erase operations which are described in detail in the following sections. during a write operation, the system must drive ce# and we# to vil and oe# to vih when providing address, command, and data. addresses are latched on th e last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. note the following: ? when the embedded program algorithm is complete, the device returns to the read mode. ? the system can determine the status of the program operation by readin g the dq status bits. refer to write operation status for information on these status bits. ? an 0 cannot be programmed back to a 1. a succeeding read shows that the data is still 0. ? only erase operations can convert a 0 to a 1. ? any commands written to the device during the embedded program/erase are ignored except the suspend commands. ? secured silicon sector , autoselect, and cfi functions are unavailable when a program operation is in progress. ? a hardware reset and/or power rem oval immediately terminates the program/erase operation and the program/erase command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity. ? programming is allowed in any sequence and across sector boundaries for single word programming operation. ? programming to the same word address multiple times without intervening erases is permitted.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 19 is29gl256 h/l single word programming single word programming mode is one method of programming the flash. in this mode, four flash command write cycles are used to program an individual flash address. the data for this programming operation could be 8 or 16 - bits wide. while the single word programming method is supported by most devices, in general single word programming is not recommended for devices that support write buffer programming. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the pro gram operation by reading the dq status bits. ? during programming, any command (except the suspend program command) is ignored. ? the secured silicon sector , autoselect, and cfi functions are unavailable when a program operation is in progress. ? a hardware re set immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming to the same address multiple times continuously (for example, walking a bit within a word) is permitted.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 20 is29gl256 h/l figure 4. single word program
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 21 is29gl256 h/l write buffer programming write buffer programming allows the system to write a maximum of 256 words in one programming operation. this results in a faster effective word programming time than the standard word programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming occurs. at this point, the system writes the number of word locations minus 1 that are loaded into the page buffer at the sector address in which programming occurs. this tells the device how ma ny write buffer addresses are loaded with data and therefore when to expect the program buffer to flash confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. (number loaded = the number of locations to program minus 1. for example, if the system programs 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starting address is the first address/data pair to be pro grammed, and selects the write - buffer - page address. all subsequent address/data pairs must fall within the elected - write - buffer - page. the write - buffer - page is selected by using the addresses a23 C a 8 . the write - buffer - page addresses must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write - buffer - pages. this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected write - buffer - page, the operation aborts.) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. note that if a write buffe r address location is loaded multiple times, the address/data pair counter is decremented for every data load operation. also, the last data loaded at a location before the program buffer to flash confirm command is the data programmed into the device. it is the software's responsibility to comprehend ramifications of loading a write - buffer location more than once. the counter decrements for each data load operation, not for each unique write - buffer - address location. once the specified number of write b uffer locations have been loaded, the system must then write the program buffer to flash command at the sector address. any other address/data write combinations abort the write buffer programming operation. the write operation status bits should be used while monitoring the last address location loaded into the write buffer. this eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, a nd then check the write operation status at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the device status during write buffer programming. the write - buffer embedded programming operation can be suspended or resumed us ing the standard suspend/resume commands. upon successful completion of the write buffer programming operation, the device returns to read mode. the write buffer programming sequence is aborted under any of the following conditions: ? load a value that is g reater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write - buffer - load command. ? write an address/data pair to a different write - buffer - page than the o ne selected by the starting address during the write buffer data loading stage of the operation. ? writing anything other than the program to buffer flash command after the specified number of data load cycles.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 22 is29gl256 h/l the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, dq5 = 0. this indicates that the write buffer programming operation was aborted. note th at the secured silicon sector , a utoselect, and cfi functions are unavailable when a program ope ration is in progress. write buffer programming is allowed in any sequence of memory (or address) locations. these flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. use of the write buffer is strongly recommended for programming when multiple words are to be programmed. figure 5. write buffer programming operation
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 23 is29gl256 h/l sector erase sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un - lock cycles, followed by a set - up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the sector erase suspend command is valid. all other commands are ignored. if there are several sectors to be erased, sector erase comman d sequences must be issued for each sector. that is, only a sector address can be specified for each sector erase command. users must issue another sector erase command for the next sector to be erased after the previous one is completed. when the embedde d erase algorithm is complete d , the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to write operation status for information on these s tatus bits. flowchart on figure 6 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ac characteristics section for parameters, and to the sector erase operations timing diagram for timing waveforms. figure 6. sector erase operation start write erase command sequence data poll from system or toggle bit successfully completed erase done data =ffh? yes no
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 24 is29gl256 h/l chip erase command sequence chip erase is a six - bus cycle operation as indicated by table 1 3 . these commands invoke the embedded erase algorithm, which does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory to an all zero data pattern prior to electrical erase. after a successful chip erase, all locations of the chip contain ffffh. the system is not required to provide any controls or timings during these operations. when the embedded erase algorithm is co mplete, that sector returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to write operation status for information on these status bits. any commands writ ten during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that sector has returned to reading array data, to e nsure the entire array is properly erased. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the sector address is required when writing this command. this command is valid only during the sector erase operation. the sector erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are dont - cares whe n writing the sector erase suspend command. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the device enter s the erase - suspend - read mode. the system can read data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) reading at any address within erase - suspended sectors produces status infor mation on dq7 - dq0. the system can use dq7, or dq6, and dq2 together, to determine if a sector is actively erasing or is erase - suspended. after an erase - suspended program operation is complete, the device returns to the erase - suspend - read mode. the system can determine the status of the program operation using write operation status bits, just as in the standard program operation. in the erase - suspend - read mode, the system can also issue the autoselect command sequence , the secured silicon sector command , and cfi query command . refer to write buffer programming and the autoselect for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase - suspended sector is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 25 is29gl256 h/l program suspend/program resume commands the program suspend command allows the system to interrupt an embedded programming operation or a write to buffer programming operation so that data can read from any non - suspended sector. when the program suspend command is written during a programming process, the device halts the programming operation within 15 s maximu m (5 s typical) and updates the status bits. addresses are don't - cares when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non - suspended sector. the program suspend comma nd may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not within a sector in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence and cfi query command when the device is in program suspend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to program suspend mode, and is ready for another valid operation. after the program resume command is written, the d evice reverts to programming. the system can determine the status of the program operation using the write operation status bits, just as in the standard program operation. the system must write the program resume command (address bits are don't care) to exit the program suspend mode and continue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resumed programming. accelerated program accelerated si ngle word programming and write buffer programming operations are enabled through the wp#/acc pin. this method is faster than the standard program command sequences. if the system asserts v hh on this input, the device automatically enters the accelerated program mode and uses the higher voltage on the input to reduce the time required for program operations. the system can then use the write buffer load command sequence provided by the accelerated program mode . note that if a write - to - buffer - abort reset is required while in accelerated program mode , the full 3 - cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded program operation, returns the device to normal operation. ? sectors must be unlocked prior to raising wp#/acc to v hh . ? the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. ? it is recommended that wp#/acc apply v hh after power - up sequence is completed. in addition, it is recommended that wp#/acc apply from v hh to vih/vil before powering down v cc / v io .
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 26 is29gl256 h/l write operation status the device provides several bits to determine the status of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whe ther the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. note that the data# polling is valid only for the last word being programmed in the write - buffer - page during write buffer prog ramming. reading data# polling status on any word other than the last word to be programmed in the write - buffer - page returns false status information. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active, then that sector returns to the read mode. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously w ith dq6 - dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6 - dq0 may be still invalid. valid data on dq7 - d00 appears on successive read cycles.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 27 is29gl256 h/l figure 7 . write operation status flowchart dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time - out. during an embedded program or erase algorithm operation, successive read cycles to any address that is being programmed or erased causes dq6 to toggle. when the operation is complete, dq6 stops toggling.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 28 is29gl256 h/l after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100s, then returns to reading array data. if not all selected sectors are protect ed, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase 2 suspended. when the device is acti vely erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase - suspended. alternativ ely, the system can use dq7. if a program address falls within a protected sector, dq6 toggles for approximately 1s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase - suspend - program mode, and stops toggling once the embedded program algorithm is complete. toggle bit i on dq6 requires either oe# or ce# to be de - asserted and reasserted to show the change in state. dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase - suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles whe n the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase - suspended. dq6, by comparison, indicates whether the device is actively erasing, or is i n erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit status, it must read dq7 C dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erases operation. the system can read array data on dq7 C dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the to ggle bit is still toggling, the system also should note whether the value of dq5 is high. if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the togg le bit is no longer toggling, the device has successfully completed the program or erases operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array dat a. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in th e previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. note when verifying the status of a write operation (embedded program/erase) of a memory sector, dq6 and dq2 toggle between high and low states in a series of consecutive and contiguous status read cycles. in order for this toggling behavior to be properly observed, the consecutive status bit read s must not be interleaved with read accesses to other memory sectors. if it is not possible to temporarily prevent reads to other memory sectors, then it is recommended to use the dq7 status bit as the alternative method of determining the active or inacti ve status of the write operation.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 29 is29gl256 h/l dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1, indicating that the program or erase cycle w as not successfully completed. the device does not output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1, while any other bits that were correctly requested to be changed from 1 to 0 are programmed. attempting to program a 0 to a 1 is masked during the programming operation. under valid dq5 cond itions, the system must write the reset command to return to the read mode (or to the erase - suspend - read mode if a sector was previously in the erase - suspend - program mode). dq3: sector erase timeout state indicator after writing a sector erase command se quence, the output on dq3 can be check ed to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) when sector erase starts, dq3 switches from 0 to 1 . this device does not support multi ple sector erase (continuous sector erase) command sequences so it is not very meaningful since it immediately shows as a 1 after the first 30h command. future devices may support this feature. dq1: write to buffer abort dq1 indicates whether a write to buffer operation was aborted. under these conditions dq1 produces a 1. the system must issue the write to buffer abort reset command sequence to return the device to reading array data. table 5 . write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program suspend read program suspended sector invalid (not allowed) 1 non - program suspended sector data 1 erase suspend mode erase suspend read erase suspended sector 1 no toggle 0 n/a toggle n/a 1 non - erase suspended sector data 0 erase suspend program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write to buffer busy(note 3) dq7# toggle 0 n/a n/a 0 0 abort(note 4) dq7# toggle 0 n/a n/a 1 0 notes 1. dq5 switches to 1 when an embedded program, embedded erase, or write - to - buffer operation has exceeded the maximum timing limits. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write - buffer address location. 4. dq1 switches to 1 when the device has aborted the w rite - to - buffer operation
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 30 is29gl256 h/l writing commands/command sequences during a write operation, the system must drive ce# and we# to vil and oe# to vih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an erase operation can erase one sector or the entire device. table 3 indicate s the address space that each sector occupies. the device address space is divided into uniform 64kw/128kb sectors. a sector address is the set of address bits required to uniquely select a sector. icc2 in dc characteristics represents the active current specification for the write mode. ac characteristics contains timing specification tables and timing diagrams for w rite operations. ry/by# the ry/by# is a dedicated, open - drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by # is an open - drain output, several ry/by# pins can be tied together in parallel with a pull - up resistor to v cc . this feature allows the host system to detect when data is ready to be read by simply monitoring the ry/by# pin, which is a dedicated output and controlled by ce# (not oe#). hardware reset the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of trp (reset# pulse width), the device immediately terminates any ope ration in progress, tri - states all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. to ensure data integrity prog ram/erase operations that were interrupted should be reinitiated once the device is ready to accept another command sequence. when reset# is held at vss, the device draws v cc reset current (icc5). if reset# is held at vil, but not at vss, the standby curr ent is greater. reset# may be tied to the system reset circuitry which enables the system to read the boot - up firmware from the flash memory upon a system reset.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 31 is29gl256 h/l software reset software reset is part of the command set that also returns the device to array read mode and must be used for the following conditions: 1. t o exit autoselect mode 2. w hen dq5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. e xit sector lock/unlock operation. 4. t o return to erase - suspend - read mode if the device was previously in erase suspend mode. 5. a fter any aborted operations the following are additional points to consider when using the reset command: ? this command resets the sectors to the read and address bits are ignored. ? reset commands are ignored during program and erase operations. ? the reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). this r esets the sector to which the system was writing to the read mode. ? if the program command sequence is written to a sector that is in the erase suspend mode, writing the reset command returns that sector to the erase - suspend - read mode. ? the reset command may be written during an autoselect command sequence. ? if a sector has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that sector to the erase - suspend - read mode. ? if dq1 goes high during a write buffer programming operation, the system must write the write to buffer abort reset command sequence to reset the device to reading array data. the standard reset command does not work during this condition. advanced sector protection/unprotection the advanced sector protection/unprotection feature disables or enables programming or erase operations , individually, in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. this section describes the variou s methods of protecting data stored in the memory array. an overview of these methods is shown in figure 8 . every main flash array sector has a non - volatile (ppb) and a volatile (dyb) protection bit associated with it. when either bit is 0, the sector is protected from program and erase operations. the ppb bits are protected from program and erase when the ppb lock bit is 0. there are two methods for managing the state of the ppb lock bit, persistent protection and password protection. the persistent pro tection method sets the ppb lock to 1 during power up or r eset so that the ppb bits are unprotected. there is a command to clear the ppb lock bit to 0 to protect the ppb bits. there is no command in the persistent protection method to set the ppb lock bit therefore the ppb l ock bit will remain at 0 until the next power - off or reset. the persistent protection method allows boot code the option of changing sector protection by programming or erasing the ppb, then protecting the ppb from further change for th e remainder of normal system operation by clearing the ppb lock bit. this is sometimes called boot - code controlled sector protection. the password method clears the ppb lock bit to 0 during power up or r eset to protect the ppb. a 64 - bit password may be permanently programmed and hidden for the password method. a command can be used to provide a password for comparison with the hidden password. if the password matches the ppb lock bit is set to 1 to unprotect the ppb. a command can be used to clear the pp b lock bit to 0 .
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 32 is29gl256 h/l 1. 0 = pp b s l o c k e d , 1 = p p bs u n lock e d 2. b i t i s v o l at i le, and de f au l ts to 1 on rese t . 3. p r ogr a m m i n g to 0 lo c k s a l l p pbs t o t h eir cu r rent st a te. 4. o n ce pro g ra m m e d to 0, r eq u ires h a rdwa r e re s et to unlock p ersistent pro t ection bit (ppb) memo r y array sector 0 dyb 0 ppb lock bit ppb 0 sector 1 dyb 1 ppb 1 1 sector 2 ppb 2 2 dyb 2 dyb 3 sector 3 ppb 3 sector 2 52 sector 2 53 sector 2 54 dyb 252 dyb 253 dyb 254 sector 2 55 dyb 255 ppb 252 ppb 255 ppb 253 ppb 254 figure 8 . advanced sector protection/unprotection 5. 0 = s ector protected 1 = sector unprot e c t ed 6. dyb bits are only effective for sectors that are not protected via ppb (ppb = 1) . 7. v ol a tile bi t s : def a ul t s t o un p rote c t e d a f ter p ower up. 8 . 0 = s ector protected 1 = se ctor unprotected 9 . ppbs programmed in d ivid u al l y , b ut c l e ared c o ll e c t i v e l y. the selection of the ppb lock management method is made by programming otp bits in the lock register so as to permanently select the method used. the lock register also contains otp bits, for protecting the s ecured s ilicon r egion . the ppb bits are erased so that all main flash array sectors are unprotected when shipped from factory . the secured silicon region can be factory protected or left unprotected depending on customer request . dynamic pro t ection bit (dyb) password protection mode (dq2) persistent protection mode (dq1) lock register bits (otp) 64 - bit password (otp)
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 33 is29gl256 h/l lock register the lock register consists of 16 bits and e ach of these bits in the lock register are non - volatile otp . the factory locked secured silicon sector protection bit is dq0 and the customer locked secured silicon sector protection bit is dq 6. if dq0 is 0, it means that the factory secured silicon area is locked and if dq0 is 1, it means that it is unlocked. similarly, i f dq 6 is 0, it means that the customer secured silicon area is locked and if dq 6 is 1, it means that it is unlocked. the secure silicon sector protection b its must be used with caution, as once locked, there is no procedure available for unlocking the protected portion of the secure silicon region and none of the bits in the protected secure silicon region memory space c an be modified in any way. once the secure silicon region area is protected, any further attempts to program in the area will fail. the p ersistent protection mode lock bit is dq1 and the password protection mode lock bit is dq2. if dq1 is set to 0 , the device is used in the persistent protection mode. if dq 2 is set to 0, the device is used in the password protection mode. when shipped from the factory, a ll devices default to the persistent protection method . either dq1 or dq2 can be programmed by user . once programming one of them another one will be permanently disabled and any change is not allowed . if both dq1 and dq2 are selected to be programmed at the same time, the operation will abort. ppb protection otp bit is dq3 and dyb lock boot bit is dq4 . dq3 is programmed in the issi factory. when the device is programmed to disable all ppb erase command, dq3 outputs a 0 when the lock register bits are read. similarly, if the device is programmed to enable all ppb erase command, dq3 outputs a 1 when the lock register bits are read. likewise the dq4 bit is also programmed in the issi factory. dq4 is the bit which indicates whether volatile sector protection bit (dyb) is protected or not after boot - up. when the dev ice is programmed to set all volatile sector protection bit protected after power - up, dq4 outputs a 0 when the lock register bits are read. similarly, when the device is programmed to set all volatile sector protection bit unprotected after power - up, dq4 outputs a 1 . dq5 and dq15 ~ dq 7 are reserved and will be 1s. table 6 . lock register bit default description dq 15 ~ dq7 each bit = 1 reserved dq 6 1 customer locked secured silicon region protection bit (0 = protected, 1 = unprotected) dq 5 1 reserved dq 4 1 dyb lock boot bit 0 = protected all dyb after boot - up 1 = unprotected all dyb after boot - up dq 3 1 ppb one time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled dq 2 1 password protection mode lock bit dq 1 1 persistent protection mode lock bit dq0 0 factory locked secured silicon region protection bit (0 = protected, 1 = unprotected) notes : 1. if the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. 2. after the lock register bits command set entry command sequence is written, reads and writes for sector 0 are disabled, while reads from other sectors are allowed until exiting this mode. after selecting a sector protection method, each sector ca n operate in any of the following three states: 1. constantly locked : the selected sectors are protected and cannot be reprogrammed unless ppb lock bit is cleared via hardware reset, or power cycle. 2. dynamically locked : the selected sectors are protected and can be altered via software commands. 3. unlocked : the sectors are unprotected and can be erased and/or programmed.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 34 is29gl256 h/l persistent protection bits the persistent protection bits are unique for each sector and nonvolatile ( refer to figure 8 and table 3. s ector / persistent protection sector group address tables ) . it ha s the same endurances as the flash memory. preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. there is a command to clear the ppb lock bit to 0 to protect the ppb. however, t here is no command in the persistent protection method to set the ppb lock bit to 1 therefore the ppb lock bit will r emain at 0 until the next power up or reset. notes 1. each ppb is individually p rogrammed and all are erased in parallel. 2. while programming ppb and d ata polling on programming ppb address, array data can not be read from any sector s . 3. entry command disables reads and writes for all sector s selected. 4. reads within that sector return the ppb status for that sector. 5. all reads must be performed using the read mode. 6. the specific sector address are written at the same time as the program command. 7. if the ppb lock bit is set, the ppb program or erase command does not execute and times - out without programming or erasing the ppb. 8. there are no means for individually erasing a specific ppb and no specific sector address is required for this operation. 9. exit command must be issued after the execution which resets the device to read mode and re - enables reads and writes for all s ector s. 10. the pr ogramming state of the ppb for given sector s can be verified by writing a ppb status read command to the device as described by the flow chart shown in figure 9 . user only can use dq6 an d ry/by# pin to detect programming status.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 35 is29gl256 h/l figure 9 . ppb program algorithm note: ba = base address
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 36 is29gl256 h/l dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dybs only control the protection scheme for unprotected sectors that have their ppbs cleared (erased to 1). by issuing the dyb set or clear command sequences, the dybs are set (programmed to 0) or cleared (erased to 1), thus placing each sector in th e protected or unprotected state respectively. this feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. notes 1. the dybs can be set (programmed to 0) or cleared (erased to 1) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to 1) and upon power up or reset, the dybs can be set or cleared depending upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to 1), then the sectors may be modified depending upon the ppb state of that sector (see table 7 ). 3. the sectors would be in the protected state if the option to set the dybs after power up is chosen (programmed to 0) . 4. it is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. however, if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power - cycle, or hardware reset. the ppbs can then be changed to reflect the de sired settings. setting the ppb lock bit once again locks the ppbs, and the device operates normally again. 6. to achieve the best protection, it is recommended to execute the ppb lock bit set command early in the boot code and protect the boot code by hol ding wp#/acc = vil. note that the ppb and dyb bits have the same function when wp#/acc = vhh as they do when acc =vih. persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all sectors. when set (programme d to 0), it locks all ppbs and when cleared ( erased to 1), allows the ppbs to be changed. there is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit , but only a hardware reset or a power - up clears this bit. 2. the ppb lock bit must be set (programmed to 0) only after all ppbs are configured to the desired settings. password protection m ode the password protection m ode allows an even higher level of security than the persistent sector protection mode by requiring a 64 - bit password for unlocking the device ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bit is set 0 to maintain the password mode of operation. successful execution of the password unlock comma nd by entering the entire password clears the ppb lock bit, allowing for sector ppbs modifications. notes 1. the password program command is only capable of programming 0s. 2. the password is all 1s when shipped from factory. it is located in its own memory space and is accessible through the use of the password program and password read commands. 3. all 64 - bit password combinations are valid as a password. 4. once the password is programmed and verified, the password mode locking bit must be set in or der to prevent reading or modification of the password. 5. the password mode lock bit, once programmed, prevents reading the 64 - bit password on the data bus and further password programming. all further program and read commands to the password region are disabled (data is read as 1's) and these commands are ignored. there is no means to verify what
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 37 is29gl256 h/l the password is after the password protection mode lock bit is programmed. password verification is only allowed before selecting the password protection mode. 6. the password mode lock bit is not erasable. 7. the exact password must be entered in order for the unlocking function to occur. 8. the addresses can be loaded in any order but all 4 words are required for a successful match to occur. 9. the sector addre sses and word line addresses are compared while the password address/data are loaded. if the sector add ress don't match than the error will be reported at the end of that write cycle. the status register will return to the ready state with the program stat us bit set to 1, program status register bit set to 1, and write buffer abort status bit set to 1 indicating a failed programming operation. it is a failure to change the state of the ppb lock bit because it is still protected by the lack of a valid passwo rd. the data polling status will remain active, with dq7 set to the complement of the dq7 bit in the last word of the password unlock command, and dq6 toggling. ry/by# will remain low. 10. the specific address and data are co mpared after the program buffer to flash command has been given. if they don't match to the internal set value than the status register will return to the ready state with the program status bit set to 1 and program status register bit set to 1 indicating a failed programming operation. it is a failure to change the state of the ppb lock bit because it is still protected by the lack of a valid password. the data polling status will remain active, with dq7 set to the complement of the dq7 bit in the last word of the password unlock comman d, and dq6 toggling. ry/by# will remain low. 11. the device requires approximately 100 s for setting the ppb lock after the valid 64 - bit password is given to the device. 12. the password unlock command cannot be accepted any faster than once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64 - bit combinations in an attempt to correctly match a password. the embedded algorithm status checking methods may be used to determine when the d evice is ready to accept a new password command. 13. if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 38 is29gl256 h/l figure 10 . lock register program algorithm
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 39 is29gl256 h/l table 7 . sector protection schemes: dyb, ppb and ppb lock bit combinations table 7 contains all possible combinations of the dyb, ppb, and ppb lock bit relating to the status of the sector. in summary, if the ppb lock bit is locked (set to 0), no changes to the ppbs are allowed. the ppb lock bit can only be unlocked (reset to 1) through a hardware reset or power cycle. see also figure 8 for an overview of the advanced sector protection feature. hardware data protection methods the device offers two main types of data protection at the sector level via hardware control: ? when wp#/acc is at vil, the either the highest or lowest sector is locked (device specific). there are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. the following subsections describes these methods: wp#/acc method the write protect feature provides a hardware method of protecting one outermost sector. this function is provided by the wp#/acc pin and overrides the previously discussed sector protection/unprotection method. if the system asserts vil on the wp#/acc pin, the device disables program and erase functions in the highest or lowest sector independently of whether the sector was protected or unprotected using the method describ ed in advanced sector protection/unprotection on page 2 4 . if the system asserts vih on the wp#/acc pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. the wp#/acc pin must be held stable during a command sequence execution. wp# has an internal pull - up; when unconnected, wp# is set at vih. note if wp#/acc is at vil when the d evice is in the standby mode, the maximum input load current is increased.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 40 is29gl256 h/l low v cc write inhibit when vcc is less than vlko (lock - out voltage) , the device does not accept any write cycles. this protects data during vcc power - up and power - down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until vcc is greater than vlko. the system must provide the proper signals to the control inputs to preven t unintentional writes when vcc is greater than vlko. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. power - up write inhibit if we# = ce# = reset# = vil and oe# = vih during pow er up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power - up. power conservation modes standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are bot h held at v cc 0.3 v. the device requires standard access time (tce) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. icc4 in dc characteristics represents the standby current specification automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for tacc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. hardw are reset# input operation the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at vss 0.3 v, the device draws icc reset current (icc5). if reset# is held at vil but not within vss 0.3 v, the standby current is greater. reset# may be tied to the system reset circuitr y and thus, a system reset would also reset the flash memory, enabling the system to read the boot - up firmware from the flash memory.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 41 is29gl256 h/l output disable (oe#) when the oe# input is at vih, output from the device is disabled. the outputs are placed in the high impedance state. (with the exception of ry/by#.) secured silicon sector flash memory region the secured silicon sector provides an extra flash memory otp area that can be programmed only once and permanently protected from further changes . the secur ed silicon sector is total 128 kbytes in length and consists of 512 - byte for factory locked secured silicon region, 512 - byte for customer locked secured silicon region, and 127 - kbyte undefined region. table 8. secured silicon sector a ssignment word address range content size 0 000000h ~ 00 000 ff h factory locked area 512 bytes 0 000 100 h ~ 0 000 1f fh customer locked area 512 bytes 0000200h ~ 3ffffffh undefined 127 kbytes the secured silicon sector indicator bit s dq15 - dq0 at autoselect address 03h is used to indicate whether the secured silicon sector is factory locked/unlocked and customer locked/unlock as well as the lowest or highest address sector wp# protected as the following. secured silicon sector indicator bits secured silicon sector indicator bits description data (b = binary) dq15 ~ dq8 undefined 1 (reserved) dq7 factory locked secured silicon region 0 = unlocked 1 = locked dq6 customer locked secured silicon region 0 = unlocked 1 = locked dq5 undefined 1 (reserved) dq4 wp# protects 0 = lowest address sector 1 = highest address sector dq3 ~ dq0 undefined 1111b (reserved) please note the following general conditions: ? on power - up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads outside of sector sa0 return invalid data. reads l ocations above 1 - kbyte address of the sector sa0 return invalid data. ? sector sa0 during the secured silicon sector entry command is remapped from memory array to secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit c ommand must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible when the device i s executing an embedded program o r embedded erase algorithm. ? regardless that the sector sa 0 is suspended, if system enters secured silicon sector mode, the secured s ilicon sector region can be read . ? the acc function is not available when the secured silicon sector is enabled.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 42 is29gl256 h/l factory/ customer locked secured silicon region the customer locked secured silicon region is always shipped unprotected ( secured silicon sector indicator bit dq 6 set to 0 ), allowing customers to utilize that se ctor in any manner they choose. the factory locked secured silicon region always protected when shipped from the factory ( secured silicon sector indicator bit dq 7 set to 1 ) . it may be programmed with customer code and locked by customer request. please note the fo llowing: ? the secured silicon region can be read any number of times, but can be programmed and locked only once. the secured silicon sector lock must be used with caution , as once locked, there is no procedure available for unlocking the secured silicon se ctor area and none of the bits in the secured silicon sector memory space can be modified in any way. ? the accelerated programming (acc) is not available when the secured silicon sector is enabled. ? once the secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command sequence which return the device to the memory array at sector 0. secured silicon sector entry/exit command sequences the system can access the secured silicon sector region by issuing the three - cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four - cycle exit secured silicon sector command sequence. the secured silicon sector entry command allows the following commands to be executed ? read customer and factory secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may re ad the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the devi ce.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 43 is29gl256 h/l common flash interface (cfi) the common flash interface (cfi) specification outlines device and host systems software interrogation handshake, which allows specific vendor - specified software algorithms to be used for entire families of devices. software support can then be device - independent, jedec id - independent, and forward - and backward - compatible for the specified flash device families. flash vend o rs can standardize their existing interfaces for long - term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses give n in tables 9 ~1 2 .in word mode, the upper address bits (a 7 C msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the devic e enters the cfi query mode and the system can read cfi data at the addresses given in tables 9 ~1 2 . the system must write the reset command to return the device to the autoselect mode.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 44 is29gl256 h/l table 9 . cfi query identification string ad d resses (word mode) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists ) table 10 . system interface string addresses (word mode) data description 1bh 0027h vcc min (write/erase) dq7 - dq4: volt, dq3 - dq0: 100mv 1ch 0036h vcc max (write/erase) dq7 - dq4: volt, dq3 - dq0: 100mv 1dh 0000h vpp min voltage (00h = no vpp pin present) 1eh 0000h vpp max voltage (00h = no vpp pin present) 1fh 0003h typical timeout per single byte/word write 2 n s 20h 000 8 h typical timeout for min size buffer write 2 n s (00h = not supported) 21h 0007 h typical timeout per individual block erase 2 n ms 22h 000 8 h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max timeout for byte/word write 2 n times typical 24h 0003 h max timeout for buffer write 2 n times typical 25h 0004h max timeout per individual block erase 2 n times typical 26h 000 3 h max timeout for full chip erase 2 n times typical (00h = not supported)
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 45 is29gl256 h/l table 1 1 . device geometry definition addresses (word mode) data description 27h 0019 h device size = 2 n bytes. 2**25=32 mb= 256m b 28h 29h 0002h 0000h flash device interface description (refer to cfi publication 100); 01h = x16 only; 02h = x8/x16 2ah 2bh 000 9 h 0000h max number of byte in multi - byte write = 2 n (00h = not supported) 2ch 000 1 h number of erase block regions within device 2dh 2eh 2fh 30h 00 f fh 0000h 0000h 0002h erase block region 1 information (refer to the cfi specification of cfi publication 100) 256 uniform sectors (f fh + 1) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information (refer to the cfi specification of cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to the cfi specification of cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification of cfi publication 100) 3dh 3eh 3fh ffffh ffffh ffffh reserved
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 46 is29gl256 h/l table 1 2 . primary vendor - specific extended query ad d resses (word mode) data description 40h 41h 42h 0050h 0052h 0049h query unique ascii string "pri" 43h 0031h major version number, ascii 44h 0034 h minor version number, ascii 45h 00 11 h address sensitive unlock (bits 1 - 0) 00 = required, 01 = not required process technology (bits 5 - 2) 0001 = 0.18um, 0010 = 0.13um, 0011 = 90nm , 0100 = 65nm 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = minimum number of sectors per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 000 4 h sector protect/unprotect scheme 00h = high voltage sector protection 01h = high voltage + in - system sector protection 02h = hv + in - system + software command sector protection 03h = software command sector protection 04h = advanced sector protection method 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 000 3 h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 03 = 16 word page 4dh 0085h minimum wp#/acc (acceleration) supply voltage 00 = not supported, dq7 - dq4: volts, dq3=dq0: 100mv 4eh 0095h maximum wp#/acc (acceleration) supply voltage 00 = not supported, dq7 - dq4: volts, dq3=dq0: 100mv 4fh 00 xx h top/bottom boot sector flag 04 = uniform sectors bottom wp# protect 05 = uniform sectors top wp# protect 50h 0001h program suspend 00 = not supported, 01 = supported 52h 0009 h secured silicon sector (customer otp area) size 2 n bytes 53h 000fh hardware reset low time - out during an embedded algorithm to read mode maximum 2 n ns 54h 0009h hardware reset low time - out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend latency maximum 2 n s 56h 0005h program suspend latency maximum 2 n s 57h 0000h bank organization 00 = data at 4ah is zero, x = number of banks
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 47 is29gl256 h/l table 1 3 . is29gl256 command definitions command sequence cycles bus cycles 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle addr data add r data add r data add r data add r data add r data read 1 ra rd reset 1 xxx f0 autoselect manufacturer id word 4 555 aa 2aa 55 555 9 0 000 7f 100 9d byte aaa 555 aaa 000 7f 200 9d device id word 4 555 aa 2aa 55 555 90 x 01 22 7e x0e 2222 x0f 2201 byte aaa 555 aaa x 02 7e x1c 2 2 x1e 01 sector protect verify word 4 555 aa 2aa 55 555 90 (sa) x 02 00 01 byte aaa 555 aaa (sa) x04 00 01 program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa write to buffer word 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd byte aaa 555 program buffer to flash word 1 sa 29 byte write to buffer abort reset word 3 555 aa 2aa 55 555 f0 byte aaa 555 aaa chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase /program suspend word 1 xxx b0 byte erase /program resume word 1 xxx 30 byte secured silicon sector entry word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa secured silicon sector exit word 4 555 aa 2aa 55 555 90 xx 00 byte aaa 555 aaa cfi query word 1 55 98 byte aa accelerated program 2 xx a0 pa pd legend x = dont care ra = address of the memory to be read. rd = d ata read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the risi ng edge of the we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (i n a utoselect mode) or erased. address bits amax C a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. wc = word count is the number of write b uffer locations to load minus 1 and maximum value is 31 for word and byte mode . note: the data is 00h for an unprotected sector and 01h for a protected sector. this is same as ppb status read except that the protect and unprotect statuses are inverted here
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 48 is29gl256 h/l table 14 . is29gl256 command definitions command sequence cycles bus cycles 1 st / 7 th c ycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle addr data add r data add r data add r data add r data add r data lock register command set entry word 3 555 aa 2aa 55 555 40 byte 3 aaa aa 55 55 aaa 40 program 2 xxx a0 xxx data read 1 00 rd command set exit 2 xxx 90 xxx 00 password protection command set entry word 3 555 aa 2aa 55 555 60 byte 3 aaa aa 55 55 aaa 60 password program (1) 2 xxx a0 pwax pwdx pa ssword read (2) 4 00 pwd0 01 pwd 1 02 pwd 2 03 pwd 3 pa ssword unlock (2) 7 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 00 29 command set exit 2 xxx 90 xxx 00 glo ba l non - volatile ppb command set entry word 3 555 aa 2aa 55 555 c0 byte 3 aaa aa 55 55 aaa c0 ppb program 2 xxx a0 sa 00 all ppb erase 2 xxx 80 00 30 ppb s tatus read 1 sa rd ppb c ommand set exit 2 xxx 90 xxx 00 globa l volatile freeze ppb lock command set entry word 3 555 aa 2aa 55 555 50 byte 3 aaa aa 555 55 aaa 50 ppb lock set 2 xxx a0 xxx 00 ppb lock status read 1 xxx rd ppb lock command set exit 2 xxx 90 xxx 00 vol atile dyb command set entry word 3 555 aa 2aa 55 555 e0 byte 3 aaa aa 555 55 aaa e0 dyb set 2 xxx a0 sa 00 dyb clear 2 xxx a0 sa 01 dyb s tatus read 1 sa rd dyb c ommand set exit 2 xxx 90 xxx 00 legend x = dont care rd(0) = read data. sa = sector address. address bits amax C a16 uniquely select any sector. pwd = password pwdx = password word0, word1, word2, and word3. data = lock register contents: pd(0) = secured silicon sector protection bit, pd(1) = persistent protection mode lock bit, pd(2) = password protection mode lock bit. note:
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 49 is29gl256 h/l table 1 5 . dc characteristics (t a = - 40c to 12 5c; v cc = 2.7 - 3.6v) notes : 1. byte# pin can also be gnd 0.3v. byte# and reset# pin input buffers are always enabled so that they draw power if not at full cmos supply voltages. 2. maximum i cc specifications are tested with vcc = v cc max . 3. not 100% tested. symbol parameter test conditions min typ max unit i li input leakage current 0v ? v in ? vcc 1 a i lo output leakage current 0v ? v out ? vcc 1 a i cc 1 v cc active read current ce# = v il ; oe# = v ih ; v cc = v cc max 5mhz 15 30 ma 10mhz 25 45 ma i io2 v io non - active output ce# = v il , oe# = v ih 0.2 10 ma i cc 2 v cc intra - page read current ce# = v il , oe# = v ih , v cc = v cc max, f = 10 mhz 1 10 ma ce# = v il , oe# = v ih , v cc = v cc max, f = 33 mhz 5 15 i cc 3 v cc active erase/ program current ce# = v il , oe# = v ih , v cc = v cc max 20 4 0 m a i cc 4 v cc standby current ce#, reset# = vcc 0.3 v, oe# = v ih , v cc = v cc max v il = v ss + 0.3 v/ - 0.1v, 2.0 2 0 a i cc 5 v cc reset current reset# = v ss 0.3v 2.0 20 a i cc 6 automatic sleep mode v ih = vio, v i l = v ss vcc= v cc max , t acc + 30ns 50 50 0 a v ih = vio, v i l = v ss vcc= v cc max , t assb 2.0 20 a i acc acc accelerated program current ce# = v il, oe# = v ih, v cc = v cc max , wp#/acc = v hh wp#/acc pin 3 10 ma v cc pin 15 30 v il input low voltage - 0.5 0.3 x v io v v ih input high voltage 0.7 x v io v io + 0.3 v v hh acceleration program voltage 8.5 9.5 v v ol output low voltage i o l = 100 a 0.15 x v io v v oh output high voltage cmos i oh = - 100 a 0.85 x v io v v lko supply voltage (erase and program lock - out) 2.1 2.4 v
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 50 is29gl256 h/l figure 1 1 . test conditions table 1 6 . test specifications test conditions 70 ns unit vcc 2.7 - 3.6 v output load capacitance, c b l b 30 pf input rise and fall times 5 ns input pulse levels 0.0 - vio v input timing measurement reference levels 0.5vio v output timing measurement reference levels 0.5vio v c l device under test
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 51 is29gl256 h/l ac characteristics table 1 7 . read - only operations characteristics (t a = - 40c to 12 5c; v cc = 2.7 - 3.6v) parameter symbols description test setup speed unit jedec standard 70 ns t avav t rc read cycle time min 70 ns t avqv t acc address to output delay ce# = v il oe#= v il max 70 ns t elqv t ce chip enable to output delay oe#= v il max 70 ns t pacc page access time max 1 5 ns t glqv t oe output enable to output delay max 25 ns t ehqz t df chip enable to output high z max 15 ns t ghqz t df output enable to output high z max 15 ns t axqx t oh output hold time from addresses, ce# or oe# , whichever occurs first min 0 ns t oeh output enable hold time read min 0 ns toggle and data # polling min 10 n s notes: 1. high z is not 100% tested. figure 1 2 . ac waveforms for read operations addresses ce# oe# we# outputs r eset # ry/by# t b acc 0v high z output valid t b ce b t b oh t b df t b oeh b high z t b oe b t b rc b addresses stable
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 52 is29gl256 h/l figure 1 3 . page read operation timings note: addresses are a2:a - 1 for byte mode. a23
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 53 is29gl256 h/l ac characteristics table 1 8 . hardware reset (r eset #) parameter std description test setup speed unit 70 ns t rp1 reset# pulse width (during embedded algorithms) min 200 n s t rp2 reset# pulse width (not during embedded algorithms) min 2 00 n s t rh reset# high time before read min 50 n s t rb1 ry/by# recovery time ( to ce#, oe# go low) min 0 n s t rb2 ry/by# recovery time ( to we# go low) min 50 n s t ready1 reset# pin low (during embedded algorithms ) to read or write max 20 u s t ready2 reset# pin low (not during embedded algorithms ) to read or write max 500 n s figure 1 4 . ac waveforms for reset# reset# timings c e # , o e # w e # r y / b y # r e s e t # t r p 1 t r e a d y 1 t r b 2 t r b 1 r e s e t t i m i n g d u r i n g e m b e d d e d a l g o r i t h m s
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 54 is29gl256 h/l ac characteristics table 1 9 . word / byte configuration (b yte #) std parameter description test setup speed unit 70 ns t bcs byte# to ce# switching setup time min 0 ns t cbh ce# to byte# switching hold time min 0 ns t rbh ry/by# to byte# switching hold time min 0 ns r e s e t # r y / b y # c e # , o e # t r e a d y 2 t r h t r p 2 r e s e t t i m i n g n o t d u r i n g e m b e d d e d a l g o r i t h m s
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 55 is29gl256 h/l figure 1 5 . ac waveforms for byte# byte # timings for read operations byte # timings for write operations note: switching byte# pin not allowed during embedded operations c e# we # t bcs byte # t rbh ry/by # t cbh t bcs ce # oe # byte #
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 56 is29gl256 h/l a c characteristics table 20 . write (erase/program) operations parameter symbols description speed unit jedec standard 70 ns t avav t wc write cycle time min 70 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeh output enable hold time read mi n 0 ns toggle and data# polling min 10 ns t ghwl t ghwl read recovery time before write ( oe# high to we# low) min 0 ns t elwl t cs ce# setuptime min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 2 5 ns t whdl t wph write pulse width high min 20 ns t whwh1 t whwh1 write buffer program operation (note 2, 3) typ 160 s programming operation (word and byte mode) typ 8 s max 200 s t whwh2 t whwh2 sector erase operation typ 0. 1 s max 2 s chip erase operation typ 30 s t vhh v hh rise and fall time min 2 50 n s t vcs vcc setup time min 50 s t b busy we# high to ry/by# low m ax 70 ns t rb recovery time from ry/by# min 0 ns notes: 1. not 100% tested. 2. see table.2 2 erase and programming performance for more information. 3. for 1~256 words program .
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 57 is29gl256 h/l ac characteristics table 21 . write (erase/program) operations alternate ce# controlled writes parameter symbols description speed unit jedec standard 70 ns t avav t wc write cycle time min 70 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write ( oe# high to ce# low) min 0 ns t wlel t ws we# setuptime min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp write pulse width min 35 ns t ehel t cph write pulse width high min 20 ns t whwh1 t whwh1 write buffer program operation (note 2, 3) typ 160 s programming operation ( word and byte mode) typ 8 s max 200 s t whwh2 t whwh2 sector erase operation typ 0. 1 s max 2 s notes: 1. not 100% tested. 2. see table.2 2 erase and programming performance for more information. 3. for 1~ 256 word s bytes programmed.
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 58 is29gl256 h/l ac characteristics figure 1 6 . ac waveforms for chip/sector erase operations timings notes: 1. sa=sector address (for sector erase), va=valid address for reading status, d out =true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. 10 for c hip e rase t dh t ds 0x55 0x 30 status d out t whwh2 v cc address es es ce# oe# we# data ry/by# t ch t ghw l t c s t wp h t wp t bus y t rb t vcs erase command sequence (last 2 cycles) read status data (last two cycles) t ah t wc 0x2aa sa va va t as 0x555 for chip erase
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 59 is29gl256 h/l figure 17 . program operation timings notes: 1. pa=program address, pd=program data, d out is the true data at the program address. 2. v cc shown in order to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t vcs t whwh1 t busy t ds t dh d out status pd oxa0 t rb t ah t as t wc 0x555 pa pa pa program command sequence (last 2 cycles) program command sequence (last 2 cycles) t ghwl data ry/by# v cc we# addresses ce# oe# t ch t wph t cs t wp
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 60 is29gl256 h/l figure 18 . ac waveforms for /data polling during embedded algorithm operations notes: 1. va=valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle. figure 1 9 . ac waveforms for toggle bit during embedded algorithm operations figure 20 . alternate ce# controlled write operation timings t bu sy t oeh t df t oe t ce t ch t acc t rc va va va t oh valid data true complement comple - ment status data status data true valid data ce# addresses oe# we# dq[7] dq[6:0] ry/by# t ce t oe t ch valid data valid status valid status valid status (first read) (second read) (stops toggling) addresses ce# oe# we# dq6, dq2 ry/by# t rc t acc va va va va t oeh t df t oh t busy
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 61 is29gl256 h/l notes: pa = address of the memory location to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d out = array data read at va shown above are the last two cycles of the program or erase command sequence and the last status read cycle reset# shown to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 21 . dq2 vs. dq6 we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read t rh t wh t ghel t cp pd for program 0x30 for sector erase 0x10 for chip erase 0xa0 for program 0x55 for erase d out status t busy t ds t dh t cph t ws t whwh1 / t whwh2 addresses we# oe# ce# data ry/by # reset# t ah t as t wc va pa for program sa for sector erase 0x555 for chip erase 0x555 for program 0x2aa for erase
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 62 is29gl256 h/l table 2 2 . erase and programm ing performance parameter limits comments typ max unit sector erase time 0. 1 2 sec excludes 00 h programming prior to erasure chip erase time 3 0 24 0 sec byte programming time 8 200 s excludes system level overhead word programming time 8 200 s chip programming time byte 134.4 800 sec word 67.2 400 total write buffer time 160 1000 s acc total write buffer time 60 400 erase/program endurance 100k cycles minimum 100k cycles note s : 1. typical program and erase times assume the following conditions: room temperature, 3v and check er board pattern programmed. 2. maximum program and erase times assume the following conditions: worst case vcc, 90 c and 100,000 cycles. table 2 3 . 56 - pin tsop pin capacit ance @ 25c, 1.0mh z parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf note: test conditions are temperature = 25c and f = 1.0 mhz. table 2 4 . data retention parameter description test conditions min unit data retention time 150c 10 years 125c 20 years
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 63 is29gl256 h/l a bsolute maximum ratings parameter value storage temperature - 6 5 o c to +1 5 0 o c plastic packages - 6 5 o c to +1 25 o c ambient temperature with power applied - 6 5 o c to +1 25 o c surface mount lead soldering temperature standard package 240 o c 3 seconds lead - free package 260 o c 3 seconds output short circuit current 1 200ma voltage with respect to ground a9 and wp#/acc 2 - 0.5v to 9.5 v all other pins 3 - 0.5v to v cc + 0.5v vcc, vio - 0.5v to + 4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on a9 and wp#/acc pins is C 0.5v. during voltage transitions, a9 and wp#/acc pins may undershoot v ss to C 1.0v for periods of up to 50ns and to C 2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on a9 and wp#/acc is 8 .5v which may overshoot to 9 .5v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is C 0.5 v. during voltage transitions, inputs may undershoot v ss to C 1.0v for periods of up to 50ns and to C 2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may oversho ot to v cc + 2.0 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditi ons up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges p 1 p parameter value ambient operating temperature (t a ) extended grade - 4 0 c to 105 c v grade: hybrid flow - 40c to 125c automotive grade a1 - 40c to 85c automotive grade a2 - 40c to 105c automotive grade a3 - 40c to 125c v cc power supply 2.7 v ( v cc min ) C 3.6 v ( v cc max ); 3.3v (typ) v io power supply 1.65v (v io min ) C vccmax+0.2v (v io max ); 1.8v (typ) note 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. maximum negative overshoot maximum positive overshoot waveform waveform vcc +2.0 v
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 64 is29gl256 h/l figure 2 2 . 56 l tsop 1 4 mm x 20mm package outline min. nor max a - - - - - - 1.20 a1 0.05 - - - 0.15 a2 0.95 1.00 1.05 d - - - 20.00 - - - d1 - - - 18.40 - - - e - - - 14.00 - - - e - - - 0.50 - - - b 0.17 0.22 0.27 l 0.5 0.60 0.70 r 0.08 0.15 0.20 0 0 3 0 5 0 note : 1. coplanarity: 0.1 mm symbol dimension in mm
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 65 is29gl256 h/l figure 2 3 . 64 - ball ball grid array ( bga), 11 x13 mm, pitch 1mm package outline min. nor max a - - - - - - 1.40 a1 0.40 0.50 0.60 a2 0.60 0.66 0.76 d 12.90 13.00 13.10 e 10.90 11.00 11.10 d1 - - - 7.00 - - - e1 - - - 7.00 - - - e - - - 1.00 - - - b 0.50 0.60 0.70 dimension in mm symbol
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 66 is29gl256 h/l figure 2 4 . 64 - ball ball grid array ( bga), 9 x 9 mm, pitch 1mm package outline
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 67 is29gl256 h/l figure 2 5 . 56 - ball ball grid array (bga), 7 x 9 mm, pitch 0.8 mm package outline
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 68 is29gl256 h/l ordering information is29gl256 h - 70 s l e temperature range e = extended ( - 40 c to + 10 5 c ) v = hybrid flow ( - 40 c to +125 c ) a1 = automotive grade ( - 40 c to + 8 5 c) a2 = automotive grade ( - 40 c to + 10 5 c) a3 = automotive grade ( - 40 c to +125 c) packaging content l = rohs compliant package s = 56 - pin tsop g = 64 - b all bga 1 .0mm pitch, 11 mm x 13 mm f = 64 - b all bga 1 .0mm pitch, 9 mm x 9 mm d = 56 - b all bga 0 .8 mm pitch, 7 mm x 9 mm speed 70 = 70ns sector for write protect (wp#/acc= l ) h = highest address sector protected l = lowest address sector protected base part number is = integrated silicon solution inc. 29 gl = flash, 3v page mode flash memory 256 = 256 megabit ( 32 m x 8 / 16 m x 16)
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 69 is29gl256 h/l note: 1. a* = a1, a2, a3 : meets aec - q100 requirements with ppap, v = hybrid flow non - auto qualified . temp grades: e= - 40 to 105 o c , v= - 40 to 125 o c , a1= - 40 to 85 o c , a2= - 40 to 105 o c , a3= - 40 to 125 o c density speed order part number (1) sector for write protect (wp#/acc=l) packag e 256mb 70ns is29gl256h - 70sle is29gl256h - 70sl v high 56 - pin tsop is29gl256h - 70gle is29gl256h - 70gl v high 64 - ball bga ( 11x13 mm) is29gl256h - 70 f le is29gl256h - 70 f l v high 64 - ball bga ( 9x9 mm) is29gl256h - 70 d le is29gl256h - 70 d l v high 56 - ball bga ( 7x9 mm) is29gl256h - 70sl a* high 56 - pin tsop is29gl256h - 70gl a* high 64 - ball bga ( 11x13 mm) is29gl256h - 70 f l a* high 64 - ball bga ( 9x9 mm) is29gl256h - 70 d l a* high 56 - ball bga ( 7x9 mm) is29gl256h - 70 w l e high kgd (call factory) is29gl 256l - 70sle is29gl 256l - 70sl v low 56 - pin tsop is29gl 256l - 70gle is29gl 256l - 70gl v low 64 - ball bga ( 11x13 mm) is29gl 256l - 70 f le is29gl 256l - 70 f l v low 64 - ball bga ( 9x9 mm) is29gl 256l - 70 d le is29gl 256l - 70 d l v low 56 - ball bga ( 7x9 mm) is29gl 256l - 70sl a* low 56 - pin tsop is29gl 256l - 70gl a* low 64 - ball bga ( 11x13 mm) is29gl 256l - 70 f l a* low 64 - ball bga ( 9x9 mm) is29gl 256l - 70 d l a* low 56 - ball bga ( 7x9 mm) is29gl 256l - 70 w l e low kgd (call factory)
integrated silicon solution, inc. - www.issi.com rev. 00 a 08/08/2014 70 is29gl256 h/l appendix - 1 additional operating modes appendix t able 1 . additional operation modes item control input am to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 q7 ~ q0 q15 ~ q8 ce# we# oe# sector lock status verification l h l sa x v hh x l x l h l 01h or 00h (1) x read silicon id manufacturer code l h l x x v hh x l x l l l 9d h x read silicon id cycle 1 l h l x x v hh x l x l l h 7eh 22h(word), xxh (byte) cycle 2 l h l x x v hh x l x h h l 2 2h 22h(word), xxh (byte) cycle 3 l h l x x v hh x l x h h h 01h 22h(word), xxh (byte) secured silicon sector indicator bit (dq7), wp# protects highest address sector l h l x x v hh x l x l h h ffh (factory locked), 7fh (factory unlocked) bfh (customer locked), 3fh (customer unlocked) x secured silicon sector indicator bit (dq7), wp# protects lowest address sector l h l x x v hh x l x l h h e fh (factory locked), 6fh (factory unlocked) afh (customer locked), 2fh (customer unlocked) x lower software bits l h l x x v hh x l x h l l 3h x notes : 1. sector unprotected code : 00h . sector protected code : 01h . 2. factory locked /customer locked code: wp# protects highest address sector: ffh wp# protects lowest address sector: efh 3 .factory unlocked / customer locked code: wp# protects highest address sector: 7fh wp# protects lowest address sector: 6fh 4. factory locked / customer unlocked code: wp# protects highest address sector: bfh wp# protects lowest address sector: afh 5. factory unlocked / customer unlocked code: wp# protects highest address sector: 3fh wp# protects lowest address sector: 2fh 6. am: msb of address. legend l = logic low = vil, h = logic high = vih, v hh = 8.5 C 9.5v, x = dont care, sa = sector address in

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